The present invention relates to a register-controlled delay locked loop (RDLL) circuit; and, more particularly, to an RDLL circuit for reducing a chip area, which is used in a double data rate synchronous dynamic random access memory (DDR SDRAM).
Recently, the most remarkable issue in a field of DRAM development is a synchronous DRAM (SDRAM) such as a double data rate SDRAM (DDR SDRAM) and a RAMBUS DRAM. It is expected that the synchronous DRAM will lead a memory market in the future since it can perform a high-speed operation compared to a general DRAM.
The delay locked loop (DLL) represents a circuit used to synchronize an internal clock of a synchronous memory device with an external clock without errors. That is, the DLL circuit is used to synchronize the internal clock with the external clock to control a timing delay, which occurs when the external clock is used in an internal circuit.
In FIG. 1, there is provided a block diagram of a conventional register-controlled delay locked loop (RDLL) circuit.
The RDLL circuit includes a first clock buffer 101 for generating a falling clock signal fclk2, which is actuated at a falling edge of an external clock signal CLK, based on an inverted external clock signal /CLK; a second clock buffer 102 for producing a rising clock signal rclkt2, which is activated at a rising edge of the external clock, based on the external clock signal CLK; a clock divider 103 for outputting one pulse signal per every 4 clocks based on the rising clock signal rclkt2; a first phase comparator 104 for comparing a reference signal ref from the clock divider 103 with a feedback signal feedback from a replica unit 117; a first shift controller 105 for generating a right shift signal SR_1, which controls a shift register to move to the right, by using an output of the first phase comparator 104; a first shift register 106 for adjusting an amount of delay by shifting its output signal to the right in response to the right shift signal SR_1 provided from the first shift controller 105; a first long delay line 107 for adjusting the amount of delay of the output signal of the first shift register 106 in response to an output signal delay_in of the clock divider 103; a second long delay line 108 for adjusting the amount of delay of the output signal of the first shift register 106 in response to the rising clock signal rclkt2; a third long delay line 109 for adjusting the amount of delay of the output signal of the first shift register 106 in response to the falling clock signal fclk2; a second phase comparator 110 for comparing the reference signal ref from the clock divider 103, the feedback signal feedback from the replica unit 117 and an output signal of the first shift controller 105; a second shift controller 111 for producing a left shift signal SL_s and a right shift signal SR_s, which are used to control a shift register to move to left and right, respectively, by using an output signal of the second phase comparator 110; a second shift register 112 for adjusting an amount of delay by shifting its output signal to left and right in response to the left shift signal SL_s and the right shift signal SR_s supplied from the second shift controller 111; a first short delay line 113 for adjusting the amount of delay of the output signal of the second shift register 112 in response to the output signal of the first long delay line 107; a second short delay line 114 for adjusting the amount of delay of the output signal of the second shift register 112 under the control of the output signal of the second long delay line 108; a third short delay line 115 for adjusting the amount of delay of the output signal of the second shift register 112 in response to the output signal of the third long delay line 109; a low-pass filter 116, which is actuated by a delay locked loop locking signal D11_lockz from the second shift controller 111, for counting times of result values outputted from the second phase comparator 110; the replica unit 117 for compensating a timing difference between the external clock and the internal clock by using a feedback delay signal fb_dly2 whose delay is adjusted from the first short delay line 113; and a DLL driving unit 118 for providing the output signals from the second and the third short delay lines 114 and 115 to an internal circuit.
The operation of the RDLL circuit in FIG. 1 will be briefly explained hereinafter.
The clock divider 113 generated the reference signal ref and the delay line input signal delay_in, which are activated for every 4 clocks, by receiving the rising clock signal rclkt2 provided from the outside. The reference signal ref is compared with the feedback signal feedback representing a modeling result of a time delay to be compensated through the replica unit 117. The delay line input signal delay_in is inputted to the first long delay line 107 and has a delay adjusted by the first shift register 106. The output signal of the first long delay line 107 is transferred via the second short delay line 113 and the replica unit 117, and then enables the feedback signal feedback.
The feedback signal feedback outputted from the replica unit 117 is compared with a rising edge of the reference signal ref at the first and the second phase comparator 104 and 110. Then, the first shift and the second shift controller 105 and 111 generate the right shift signals SR_1 and SR_s and the left shift signal SL_1, respectively, based on the compared results from the first and the second phase comparator 104 and 110.
In FIG. 2, there is described a block diagram of the delay lines 107 to 109 and 113 to 115 employed in the conventional RDLL circuit.
Each delay unit included in the conventional delay lines includes a first NAND gate 201 for performing a NAND operation based on a rising clock signal and the output signal of the shift register; a second NAND gate 202 for executing a NAND operation based on an output signal of the first NAND gate 201 and a first input signal; a first inverter 203 for inverting an output signal of the second NAND gate 202; a third NAND gate 204 for carrying out a NAND operation based on the rising clock signal and the output signal of the shift register; a fourth NAND gate 205 for performing a NAND operation based on an output signal of the third NAND gate 204 and an output signal of the first inverter 203; a second inverter 206 for inverting an output signal of the fourth NAND gate 205; a fifth NAND gate 207 for executing a NAND operation based on a falling clock signal and the output signal of the shift register; a sixth NAND gate 208 for carrying out a NAND operation based on an output signal of the fifth NAND gate 207 and the first input signal; a third inverter 209 for inverting an output signal of the sixth NAND gate 208; a seventh NAND gate 210 for performing a NAND operation based on the falling clock signal and the output signal of the shift register; an eight NAND gate 211 for executing a NAND operation based on an output signal f the seventh NAND gate 210 and an output signal of the third inverter 209; a fourth inverter 212 for inverting an output signal of the eight NAND gate 211; a ninth NAND gate 213 for carrying out a NAND operation based on a delay signal and the output signal of the shift register; a tenth NAND gate 214 for performing a NAND operation based on an output signal of the ninth NAND gate 213 and the first input signal; a fifth inverter 215 for inverting an output signal of the tenth NAND gate 214; an eleventh NAND gate 216 for executing a NAND operation based on the delay signal and the output signal of the shift register; a twelfth NAND gate 217 for carrying out a NAND operation based on an output signal of the eleventh NAND gate 216 and an output signal of the fifth inverter 215; and a sixth inverter 218 for inverting an output signal of the twelfth NAND gate 217.
Herein, the clock signal generated by the replica unit 117 and the delay line for the reference signal ref is delayed as much as the sum of the delays. Namely, when the reference signal ref corresponds to a rising edge of the output signal of the replica unit 117, the following equation EQ. 1 is satisfied.
D+R=2t, D=2Txe2x88x92Rxe2x80x83xe2x80x83EQ. 1 
wherein D is the amount of delay of the delay line; R represents the amount of delay of the replica unit 117; and T shows a period of the external clock.
Therefore, the clock signal outputted from the delay line has a negative delay being xe2x80x98Rxe2x80x99 faster than the period of the external clock.
However, since the conventional RDLL circuit uses the delay line which occupies most of layout area of a DLL device, the chip size becomes bigger and, thus, it is difficult to design a portable DLL device. Furthermore, the current consumption is substantial because of the use of a lot of delay circuits.
It is, therefore, an object of the present invention to provide an RDLL circuit for area reduction by decreasing additional circuits of delay lines to reduce the layout area and the current consumption.
In accordance with an aspect of the present invention, there is provided a register-controlled delay locked loop (RDLL) circuit for area reduction, including: a first clock buffer for generating a falling clock signal, which is activated at a rising edge of an inverted external clock signal; a second clock buffer for generating a rising clock signal, which is activated at a rising edge of an external clock signal; a clock multiplexer for outputting a single clock signal made by combining the falling clock signal and the rising clock signal; a delay line for delaying the single clock signal to generate a delayed single clock signal; and a controller for controlling the delay line so as to adjust amount of delay of the single clock signal.
In accordance with another aspect of the present invention, there is provided a double data rate synchronous dynamic random access memory (DDR SDRAM) having a register-controlled delay locked loop (RDLL) for area reduction, the RDLL increasing: a first clock buffer for generating a falling clock signal, which is activated at a rising edge of an inverted external clock signal; a second clock buffer for generating a rising clock signal, which is activated at a rising edge of an external clock signal; a clock multiplexer for outputting a single clock signal made by combining the falling clock signal and the rising clock signal; a delay line for delaying the single clock signal to generate a delayed single clock signal; and a controller for controlling the delay line so as to adjust amount of delay of the single clock signal.